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1 quicklogic ql80fc programmable fibre channel endec ql80fc - quickfc tm rev a ql80fc - quickfc features ansi fibre channel (fc) compatibility data rates up to 2.5 gb/s supported 2.5gb/s simplex (200 mbyte/s) or duplex (400 mbyte/s) mode compatible with standard serdes components 32 bit synchronous fifo system interface tx and rx internal fifo for system applications without external fifos selectable 20-bit/10-bit encoded transmission character interface to serdes 8b/10b encoding/decoding crc calculation and checking per fc standard fibre channel loss of synchronization (los) state machine support for arbitrated loops intraframe idles support for proprietary links ?raw? data path for the injection of encoding and crc errors into the bitsteam for use in testing link error handling functions 3.3v operating voltage 3.3v cmos i/o, 5.0v cmos tolerant inputs 208 pqfp and 456 pbga packages available extended features extended features that can be designed into the user customizable logic: fibre channel link control state machine (lcsm) rrdy credit management for link flow control microprocessor interface to configure various link modes bist functions support link bit error rate measurements f eatures e xtended f eatures dual port sram 22 blocks (total of 25,344 bits) of dual-port ram configurable as ram, rom or fifo can be configured as two internal fifos of up to 352 x 36 in size configurable ram array sizes (by 2, 4, 9, 18) <5ns access times, 160+mhz fifos high speed customizable logic up to 269 customizable i/o pins 751 logic cells 300 mhz 16-bit counters, 400 mhz data paths mux-based architecture; non-volatile technology completely customizable for any digital application fibre channel block diagram d ual p ort sram h igh s peed c ustomizable l ogic ram blocks 22 blocks (25k bits) io pins fibre channel endec customizable logic cells io pins transmit receive 10 bit/20 bit 10 bit/20 bit io pins
2 preliminary 2 ql80fc - quickfc tm figure 1. system level diagram general description the ql80fc device in the quicklogic quickfc esp (embedded standard product) family provides a com- pletely integrated configurable fibre channel encoder/decoder interface solution combined with customizable logic. this device provides a means to receive and transmit high-speed serial data and implement a fibre channel link interface or any proprietary high-speed serial link. the chip is divided into two main portions, an embedded design and a customizable design. the embedded design contains the built in functionality of fibre channel's fc-1 and fc-2 layers, which the sys- tem designer uses as a standard product. this portion can not be modified. as such, all functionality and timing requirements have been verified in hardware and are guaranteed. the customizable portion consists of user customiz- able system gates, and interfaces directly to the embedded portion of the chip. these gates may be programmed to implement glue logic to other bus standards such as pci or scsi. they can also be pro- grammed with fibre channel upper layer protocols. of course, the designer may choose to modify upper layer protocols for customization. in this way, the quicklogic ql80fc provides the embedded systems designer with an easy to use and cost effective solu- tion for embedded serial applications. fibre channel application the ql80fc endec is a high performance encoder/decoder designed for use in conjunction with gb/s serdes transmitter/receiver chips. these chips, when combined with internal fifo buffer memory, can be used to build a complete serial link. optional, external fifos can be used in place of the available internal fifos to extend buffering to sizes beyond 352 words. the embedded endec is a full duplex design with an encoder section for transmission and a decoder sec- tion for reception. the transmitter/encoder section accepts a 4-byte user data word, encodes each byte into a 10-bit transmission character and outputs transmission characters to the serdes transmitter. this equals two 10-bit characters per clock (one 10- bit character per clock in 10-bit mode). the receiver/ decoder section accepts two 10-bit transmission char- system bus (optional) transmit fifo (optional) receive fifo fifo control user customizable logic embedded fibre channel endec ql80fc programmable endec chip bridge logic for data path transmit/ receive serdes 2.5 gb/s serial data over copper or optical cable internal transmit fifo internal receive fifo micro-processor or system bus interface g eneral d escription f ibre c hannel a pplications
3 ql80fc - quickfc tm acters from the serdes receiver (one 10-bit charac- ter in 10-bit mode), decodes them, and outputs a 4- byte user data word. the ql80fc has a system interface that emulates a synchronous fifo for ease of use. fifos allow maxi- mum sustained performance of 400 mb/s running a full duplex link. their function is to handle the asyn- chronous interface between the bus data rate and the different serial data rates, and handle phase and fre- quency differences inherent in serial links. internal fifos of 352 x 36 or external fifos can be used to expand the buffering to accommodate multiple frames. the ql80fc includes the hardware necessary for packetized data protection. framing functions are provided via fibre channel compliant command words (ordered sets) for start of frame and end of frame. crc generation and data frame verification protect the fibre channel frame header and data field when these framing functions are used. the device provides a microprocessor interface that allows the user to manage the serial link. signals are also provided to decode serial link error conditions and differentiate between data and commands. the ql80fc implements link synchronization with the serdes chip through the loss of synchronization state machine (los) as required by the ansi fc-ph specification. the los manages receiver word syn- chronization with the rxcomdet (comma detect) sig- nal. the ql80fc is a versatile part that allows the system designer to create proprietary or fibre channel com- pliant serial links by taking advantage of some, or all, of the fiber channel compliant features. it has a number of useful features for system designers of proprietary links. one such feature is the ability to send intraframe idles. these characters are auto- matically sent if the fifo is empty, but they do not affect the crc. in this mode the ql80fc allows simple interfacing to systems where the flow of data may be interrupted. embedded design functional description the embedded fc-1 and fc-2 layers are divided into two functional groupings: the transmit data path and the receive data path. a functional diagram for the transmit path is included in figure 2. figure 2. customizable endec chip functional block diagram - transmit and lcsm data paths e mbedded d esign f unctional d escription crc generation 8b/10b encoder user programmable logic txdata[31:0] embedded fibre channel endec registers txcrcen registers txrawen txout[19:0] txclk125_in txclk125_out txclk63 /2 txrst to receive data path txkchar async_rst tenbmode registers txrdata[39:32] async_rst tenbmode txifidleen (only [9:0] used in 10b mode) txclk63 sync reset circuit clk_rst clk_rst to receive data path
4 preliminary 4 ql80fc - quickfc tm transmit data path when the transmit data path is in standard operation (txrawen not asserted) the chip will latch an un- encoded, fibre channel, 32-bit word on inputs txdata[31:0]. this data then passes on to the 8b/ 10b encoder, which creates a 40-bit encoded fibre channel word. the encoder will encode the most sig- nificant character as a command character if the txkchar input line is asserted. this word is regis- tered and passed to the serdes in 20-bit chunks (10 bit chunks if 10 bit mode is enabled) on the txout signal lines. asserting the txcrcen signal enables the crc gen- eration block. this block will automatically detect the sof ordered set and begin crc generation using the ansi specified crc polynomial. it will continue until an eof or any other fc ordered set is encountered (unless txifidleen is asserted, then the idle ordered set will be ignored by the crc generator). it then inserts the crc value into the data path for transmis- sion to the serdes. the txrawen signal enables the raw transmit data path when asserted. in this mode, the 8 bits of txr- data is concatenated onto the 32 bits of the txdata signal to create a 40-bit wide data path. the crc generation and 8b/10b encoder blocks are bypassed and the ? raw ? data latched at the inputs is passed directly to the output registers that drive the ser- des. this mode is useful for testing the error han- dling capabilities of the serial link by providing the systems designer a way to intentionally introduce errors into the serial bit stream. the txifidleen (intra-frame idle enable) input enables the use of fibre channel idle words within a frame. when this signal is asserted, idle words present within a data frame will not affect the value generated by the crc block. this feature is useful in custom fc designs where it is desired to suspend the transmission of a frame for a period of time and then resume later. the use of external fifos is optional. there is enough ram on the endec chip to be configured into two 352 x 36 fifos. if fifos of this size are all that is required, external fifos would not be needed. synchronous read and writes directly from the system bus without a fifo is also possible. two clock signals are supplied to the customizable logic on high speed, low skew clock networks: txclk125 and txclk63. txclk125 is a clock run- ning at a maximum speed of 125 mhz, and repre- sents the ? full speed ? of the oscillator being used to clock the transmit data path. the input that drives this signal is also used to clock the serdes chip. the txclk63 clock signal operates at half the speed of the txclk125 clock. you will most likely want to use the txclk63 signal to clock your fifos and cus- tomizable logic. of course, these signals can be routed off-chip through the customizable i/o. the async_rst pin accepts an asynchronous, active high reset signal. circuitry takes this signal and syn- chronizes it with the txclk63 clock. this synchro- nous reset signal, txrst, is used to set or clear flip- flops in the transmit data path. it is made available to the user programmable logic for the same purpose on a high speed, low skew network the clk_rst input stops the txclk63 clock when this signal is asserted. this signal was added primarily to facilitate simulation. clk_rst may be permanently grounded in hardware. t ransmit d ata p ath
5 ql80fc - quickfc tm figure 3. . customizable endec chip functional block diagram - receive data path receive data path receive data path the receive data path receives encoded data from an on-board serdes, decodes it and passes the result- ing data to the customizable section of the chip. a functional block diagram of the receive data path is shown in figure 3. the rxclk125 signal latches 20 bits (10 bits when 10-bit mode is enabled) of data from the serdes into the rxin input registers on the positive edge of the clock. the rxclk125 signal is made available to the customizable section. rxclk125 is divided by two and made available to the customizable section on the rxclk63 signal line. both clocks use a high speed, low skew clock network. again you will most likely want to use the rxclk63 signal to clock all reg- isters and fifos in the receive data path. registers using rxclk125 and rxclk63 should be sensitive to the rising edge of these clocks. once the data on the rxin signal lines is latched into the input registers, the data is passed on to the 8b/ 10b decoder. under standard operation, (input rxra- wen is low), the data is decoded into 4, 8-bit charac- ters and the resulting fibre channel word is placed on the rxdata[31:0] output signals. rxrdata is not used under normal operation. if the decoder detects a fibre channel comma character in the most signifi- cant character of the word, the rxkchar signal line will be asserted. when the rxcrcen signal is asserted the crc check- ing logic will function. the crc logic will automati- cally detect a sof word and begin performing crc division on the next word in the data stream using the ansi specified crc polynomial for fibre channel. when an eof word or any other fc ordered set is detected (unless rxifidleen is asserted, then the idle ordered set will be ignored by the crc checker) the crc will assert the rxcrcrdy signal for one cycle of the rxclk63 clock. if the remainder for the division is zero, the rxcrcok signal line will also be asserted during this same cycle. user programmable logic embedded fibre channel endec rxclk125_in rxclk125_out rxclk63 /2 8b/10b decoder loss of sync state machine crc checking ordered set recognition registers rxin[19:0] rxcomdet rxlosync rxlosidx[3:0] rxdata[31:0] registers rxrawen rxkchar rxcrcok rxcrcrdy (sof, idle, eof . . . ) rxsgpbus[14:0] from transmit data path async_rst rxcrcen (only [9:0] used in 10b mode) registers rxrdata[39:32] tenbmode rxinvword rxifidleen rxclk63 sync reset circuit rxrst clk_rst from transmit data path r eceive d ata p ath
6 preliminary 6 ql80fc - quickfc tm when the rxrawen signal is asserted the ? raw ? data path will be enabled for the receive circuit. with the ? raw ? data path enabled, the data received from the serdes does not pass through the 8b/10b decoder or the crc checking blocks. instead it is routed directly to the output registers and is made available to the customizable section of the chip on signal lines rxrdata and rxdata. this mode is useful for testing the serial link. the loss of synchronization state machine is responsible for achieving character synchronization on the data being sent from the serdes. when the rst signal is asserted, the lossm goes to the ? loss of synchronization ? state. in this state the rxlosync signal will be asserted. after the reception of three valid command characters, the state machine will proceed to the ? synchronization acquired ? state and the rxlosync signal is de-asserted. after the recep- tion of 4 successive invalid characters the state machine will return to the ? loss of synchronization ? state. the value on the rxlosidx bus indicates the state of lossm. the ordered set recognition block detects fibre channel ordered sets and asserts one signal line in the rxsgpbus bus corresponding to the ordered set detected. all 15 fibre channel ordered set types are detected including sof, eof and idle. there is a list of ordered sets detected by the ordered set recogni- tion circuitry in table 1. there are two signals used to indicate that a word having a decoding error of some kind is present on the rxdata outputs. when rxinvchar is asserted a word with an invalid 10-bit representation is present on the rxdata signal lines. rxrderr indicates an invalid running disparity was detected on the cur- rently available rxdata word. the async_rst pin accepts an asynchronous, active high reset signal. circuitry takes this signal and syn- chronizes it with the rxclk63 clock. this synchro- nous reset signal, rxrst, is used to set or clear flip- flops in the receive data path. it is made available to the user programmable logic for the same purpose on a high speed, low skew network. the clk_rst input stops the rxclk63 clock when this signal is asserted. this signal was added primarily to facilitate simulation. clk_rst may be permanently grounded in hardware.
7 ql80fc - quickfc tm table of recognized ordered sets table 1. table of recognized ordered sets * only recognized when rxifidleen is asserted r ecognized o rdered s ets beginning rd identifier ordered set code hex equivalent rxsgpbus signal line asserted - sofc1 k28.5 d21.5 d23.0 d23.0 bc b5 17 17 [0] - sofi1 k28.5 d21.5 d23.2 d23.2 bc b5 57 57 [0] - sofn1 k28.5 d21.5 d23.1 d23.1 bc b5 37 37 [0] - sofi2 k28.5 d21.5 d21.2 d21.1 bc b5 55 55 [0] - sofn2 k28.5 d21.5 d21.1 d21.1 bc b5 35 35 [0] - sofi3 k28.5 d21.5 d22.2 d22.2 bc b5 56 56 [0] - sofn3 k28.5 d21.5 d22.1 d22.1 bc b5 36 36 [0] - soff k28.5 d21.5 d24.2 d24.2 bc b5 58 58 [0] - eoft k28.5 d21.4 d21.3 d21.3 bc 95 75 75 [1] + eoft k28.5 d21.5 d21.3 d21.3 bc b5 75 75 [1] - eofdt k28.5 d21.4 d21.4 d21.4 bc 95 95 95 [1] + eofdt k28.5 d21.5 d21.4 d21.4 bc b5 95 95 [1] - eofa k28.5 d21.4 d21.7 d21.7 bc 95 f5 f5 [1] + eofa k28.5 d21.5 d21.7 d21.7 bc b5 f5 f5 [1] - eofn k28.5 d21.4 d21.6 d21.6 bc 95 d5 d5 [1] + eofn k28.5 d21.5 d21.6 d21.6 bc b5 d5 d5 [1] - eofdti k28.5 d10.4 d21.4 d21.4 bc 8a 95 95 [1] + eofdti k28.5 d10.5 d21.4 d21.4 bc aa 95 95 [1] - eofni k28.5 d10.4 d21.6 d21.6 bc 8a d5 d5 [1] + eofni k28.5 d10.5 d21.6 d21.6 bc aa d5 d5 [1] - idle k28.5 d21.4 d21.5 d21.5 bc 95 b5 b5 [2] + idle* k28.5 d21.5 d21.5 d21.5 bc b5 b5 b5 [2] - r_rdy k28.5 d21.4 d10.2 d10.2 bc 95 4a 4a [3] - ols k28.5 k21.1 d10.4 d21.2 bc 35 8a 55 [4] - nos k28.5 d21.2 d31.5 d5.2 bc 55 bf 45 [5] - lr k28.5 d9.2 d31.5 d9.2 bc 49 bf 49 [6] - lrr k28.5 d21.1 d31.5 d9.2 bc 35 bf 49 [7] - arbx k28.5 d20.4 al_pa al_pa bc 4a xx xx [8] - arb(f0) k28.4 d20.4 d16.7 d16.7 bc 4a f0 f0 [8] - opnyx k28.5 d17.4 al_pd al_ps bc 91 yy xx [9] - opnyy k28.5 d17.4 al_pd al_pd bc 91 yy yy [9] - opnfr k28.5 d17.4 d31.7 d31.7 bc 91 ff ff [9] - opnyr k28.5 d17.4 al_pd d31.7 bc 91 yy ff [9] - cls k28.5 d5.4 d21.5 d21.5 bc 85 b5 b5 [10] - mrktx k28.5 d31.2 mk_tp al_ps bc 5f tt xx [11] - lip(f7,f7) k28.5 d21.0 d23.7 d23.7 bc 15 f7 f7 [12] - lip(f8,f7) k28.5 d21.0 d24.7 d23.7 bc 15 f8 f7 [12] - lip(f7,x) k28.5 d21.0 d23.7 al_ps bc 15 f7 xx [12] - lip(f8,x) k28.5 d21.0 d24.7 al_ps bc 15 f8 xx [12] - lip(y,x) k28.5 d21.0 al_pd al_ps bc 15 yy xx [12] - lpeyx k28.5 d5.0 al_pd al_ps bc 05 yy xx [13] - lpefx k28.5 d5.0 d31.7 al_ps bc 05 ff xx [13] - lpbyx k28.5 d9.0 al_pd al_ps bc 09 yy xx [14]
8 preliminary 8 ql80fc - quickfc tm dedicated i/o pins customizable interface signals s ignal d efinitions async_rst input active high, asynchronous reset txout[19:0] output data transmitted to serdes (only lines [9:0] are used in 10 bit mode) txclk125_in input transmit clock up to 125 mhz rxin[19:0] input data received from serdes rxclk125_in input receive clock up to 125 mhz rxcomdet input fibre channel comma character detected resin[2:0] input reserved for quicklogic use, hold low or high tenbmode input enables 10 bit interface to serdes when asserted clk_rst input stops txclk63 and rxclk63 when high. tie low. txrst output active high reset signal for transmit path, synchronous with txclk63 txdata[31:0] input 32 bit fibre channel word to be encoded for transmit path txrdata[39:32] input only used when txrawen is asserted. combines with txdata to construct 40 bit raw data for transmit path txcrcen input enables crc error value generation when asserted txifidleen input enables intra-frame idle support for transmit path when asserted txrawen input select between raw and encoded data modes for transmit data path txkchar input indicates that the most significant byte of data word is a k character txclk125 output full speed transmit clock up to 125 mhz (use the rising edge) txclk63 output half speed transmit clock up to 63 mhz (use the rising edge) rxdata[31:0] output 32 bit fibre channel word decoded by the endec receive path. rxrdata[39:32] output only used when rxrawen is asserted. combines with rxdata to construct 40 bit raw data through the endec receive path rxrawen input select between raw and encoded data modes for receive data path rxkchar output asserted when most significant byte of data word is a k character rxsgpbus[14:0] output bus indicating when an ordered set is detected. one signal line is asserted corresponding to the type of ordered set detected: [0] ? sof [5] ? nos [10] ? cls [1] ? eof [6] ? lr [11] ? mrk [2] ? idle [7] ? lrr [12] ? lip [3] ? r_rdy [8] ? arb [13] ? lpe [4] ? ols [9] ? opn [14] ? lpb rxcrcrdy output asserted when available data is a crc word rxcrcok output asserted when crc remainder is zero rxcrcen input enables crc error checking for the receive data path when asserted rxifidleen input enables intra-frame idle support for receive path when asserted rxlosync output asserted when bit synchronization with the serdes has been lost rxlosidx[3:0] output index indicating state of loss of sync state machine rxinvchar output asserted when available data has an invalid encoding error rxclk125 output full speed receive clock up to 125 mhz (use the rising edge) rxclk63 output half speed receive clock up to 63 mhz (use the rising edge) rxrst output active high reset signal for receive data path, synchronous with rxclk63 resout[2:0] output reserved for quicklogic use, do not connect to these outputs
9 ql80fc - quickfc tm a wide range of additional features complements the ql80fc device. the fpga portion of the device is 5-volt and 3.3-volt compliant and can perform high- speed logic functions such as 160 mhz fifos. i/o pins provide individually controlled output enables, dedicated input/feedback registers, and full jtag capability for boundary scan and test. in addition, the ql80fc device provides the benefits of non-volatil- ity, high design security, immediate functionality on power-up, and a single chip solution. the ql80fc customizable logic architecture consists of an array of user-configurable logic building blocks, called logic cells, set beneath a grid of metal wiring channels similar to those of a gate array. through vialink ? elements located at the wire intersections, the output(s) of any cell may be programmed to con- nect to the input(s) of any other cell. using the cus- tomizable logic in the ql80fc, designers can quickly and easily customize their ? back-end ? design for any number of applications. figure 4. logic cell array of logic cells the ql80fc device has 22 1,152-bit ram mod- ules, for a total of 25,344 ram bits. using two ? mode ? pins, designers can configure each module into 64 (deep) x18 (wide), 128x9, 256x4, or 512x2 blocks. see the table below. the blocks are also eas- ily cascadable to increase their effective width or depth. ram module features the ram modules are ? dual-ported ? , with com- pletely independent read and write ports and separate read and write clocks. the read ports support asynchronous and synchronous operation, while the write ports support synchronous opera- tion. each port has 18 data lines and 9 address lines, allowing word lengths of up to 18 bits and address spaces of up to 512 words. depending on the mode selected, however, some higher order data or address lines may not be used. a rray of l ogic c ells qs a1 a2 a3 a4 a5 a6 os op b1 b2 c1 c2 ms d1 e1 np e2 d2 ns f1 f3 f5 f6 f2 f4 qc qr mp az oz qz nz fz mode: address buses [a:0] data buses [w:0] 64x18 [5:0] [17:0] 128x9 [6:0] [8:0] 256x4 [7:0] [3:0] 512x2 [8:0] [1:0] ram m odule f eatures
10 preliminary 10 ql80fc - quickfc tm the write enable (we) line acts as a clock enable for synchronous write operation. the read enable (re) acts as a clock enable for synchronous read opera- tion (asyncrd input low), or as a flow-through enable for asynchronous read operation (asyn- crd input high). figure 5. ram module designers can cascade multiple ram modules to increase the depth or width allowed in single modules by connecting corresponding address lines together and dividing the words between modules. this approach allows up to 512-deep configurations as large as 16 bits wide in the ql80fc device. a similar technique can be used to create depths greater than 512 words. in this case, address signals higher than the eighth bit are encoded onto the write enable (we) input for write operations. the read data outputs are multiplexed together using encoded higher read address bits for the multiplexer select signals. jtag support jtag pins support ieee standard 1149.1a to pro- vide boundary scan capability for the ql80fc device. six pins are dedicated to jtag and program- ming functions on each ql80fc device, and are unavailable for general design input and output sig- nals. tdi, tdo, tck, tms, and trstb are jtag pins. a sixth pin, stm, is used only for program- ming. software support for the ql80fc device is available through the quick works tm development package. this turnkey pc-based quick works package, shown in figure 6, provides a complete esp software solu- tion with design entry, logic synthesis, place and route, and simulation. quick works includes vhdl, verilog, schematic, and mixed-mode entry with fast and efficient logic synthesis provided by the inte- grated synplicity synplify lite tm tool, specially tuned to take advantage of the ql80fc architecture. quick works also provides functional and timing sim- ulation for guaranteed timing and source-level debug- ging. the unix-based quick tools tm package is a subset of quick works and provides a solution for designers who use schematic-only design flow or third-party tools for design entry, synthesis, or simulation. figure 6. quickworks tool suite development tools mode[1:0] wa[a:0] wd[w:0] we wclk ram module asyncrd ra[a:0] rd[w:0] re rclk jtag s upport d evelopment t ools schematic schematic turbo hdl editor third party design entry & synthesis third party simulation vhdl/ vhdl/ verilog verilog scs tools silos iii simulator spde mixed-mode design synplify- hdl synthesis quick works design software aldec
11 ql80fc - quickfc tm ql80fc external device pins *see quicknote 65 on the quicklogic web site for information on ram initialization. ql80fc e xternal d evice p ins type description in input. a standard input-only signal. out totem pole output. a standard active output driver. t/s tri-state. a bi-directional, tri-state input/output pin. s/t/s sustained tri-state. an active low tri-state signal driven by one pci agent at a time. it must be driven high for at least one clock before being disabled (set to hi-z). a pull- up needs to be provided by the pci system central resource to sustain the inactive state once the active driver has released the sig- nal. o/d open drain. allows multiple devices to share this pin as a wired-or. pin/bus name type function vcc in supply pin. tie to 3.3v supply. vccio in supply pin for i/o. set to 3.3v for 3.3v i/o, 5v for 5.0v compliant i/o. gnd in ground pin. tie to gnd on the pcb. i/o t/s programmable input/output/tri-state/ bi-directional pin. glck/i in programmable global network or input-only pin. tie to vcc or gnd if unused. aclk/i in programmable array network or input- only pin. tie to vcc or gnd if unused. tdi/ rsi* in jtag data in/ram init. serial data in. tie to vcc if unused. connect to serial eprom data for ram init. tdo/ rco* out jtag data out/ram init clock. leave unconnected if unused. connect to serial eprom clock for ram init. tck in jtag clock. tie to gnd if unused. tms in jtag test mode select. tie to vcc if unused. trstb/ rro* in jtag reset/ram init. reset out. tie to gnd if unused. connect to serial eprom reset for ram init. stm in quicklogic reserved pin. tie to gnd on the pcb.
12 preliminary 12 ql80fc - quickfc tm pqfp 208 p inout t able 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 208 pqfp function 1 i/o 43 gnd 85 txout[4] 127 gnd 169 i/o 2 i/o 44 i/o 86 txout[5] 128 i/o 170 i/o 3 i/o 45 i/o 87 txout[6] 129 glck/i 171 i/o 4 i/o 46 i/o 88 txout[7] 130 aclk/i 172 i/o 5 i/o 47 i/o 89 txout[8] 131 vcc 173 i/o 6 i/o 48 i/o 90 txout[9] 132 resin[1] 174 i/o 7 i/o 49 i/o 91 txout[10] 133 resin[2] 175 i/o 8 i/o 50 i/o 92 txout[11] 134 vcc 176 i/o 9 i/o 51 i/o 93 txout[12] 135 i/o 177 gnd 10 vcc 52 i/o 94 txout[13] 136 i/o 178 i/o 11 i/o 53 i/o 95 gnd 137 i/o 179 i/o 12 gnd 54 tdi 96 txout[14] 138 i/o 180 i/o 13 i/o 55 rxcomdet 97 vcc 139 i/o 181 i/o 14 i/o 56 rxin[0] 98 txout[15] 140 i/o 182 gnd 15 i/o 57 rxin[1] 99 txout[16] 141 i/o 183 i/o 16 i/o 58 rxin[2] 100 txout[17] 142 i/o 184 i/o 17 i/o 59 gnd 101 txout[18] 143 i/o 185 i/o 18 i/o 60 rxin[3] 102 txout[19] 144 i/o 186 i/o 19 i/o 61 vcc 103 trstb 145 vcc 187 vccio 20 i/o 62 rxin[4] 104 tms 146 i/o 188 i/o 21 i/o 63 rxin[5] 105 i/o 147 gnd 189 i/o 22 i/o 64 rxin[6] 106 i/o 148 i/o 190 i/o 23 gnd 65 rxin[7] 107 i/o 149 i/o 191 i/o 24 i/o 66 rxin[8] 108 i/o 150 i/o 192 i/o 25 resin[0] 67 rxin[9] 109 i/o 151 i/o 193 i/o 26 txclk125_in 68 rxin[10] 110 i/o 152 i/o 194 i/o 27 vcc 69 rxin[11] 111 i/o 153 i/o 195 i/o 28 rst 70 rxin[12] 112 i/o 154 i/o 196 i/o 29 rxclk125_in 71 rxin[13] 113 i/o 155 i/o 197 i/o 30 vcc 72 rxin[14] 114 vcc 156 i/o 198 i/o 31 i/o 73 gnd 115 i/o 157 tck 199 gnd 32 i/o 74 rxin[15] 116 gnd 158 stm 200 i/o 33 i/o 75 rxin[16] 117 i/o 159 i/o 201 vcc 34 i/o 76 rxin[17] 118 i/o 160 i/o 202 i/o 35 i/o 77 rxin[18] 119 i/o 161 i/o 203 i/o 36 i/o 78 gnd 120 i/o 162 i/o 204 i/o 37 i/o 79 rxin[19] 121 i/o 163 gnd 205 i/o 38 i/o 80 txout[0] 122 i/o 164 i/o 206 i/o 39 i/o 81 txout[1] 123 i/o 165 vcc 207 tdo 40 i/o 82 txout[2] 124 i/o 166 i/o 208 i/o 41 vcc 83 vccio 125 i/o 167 i/o 42 i/o 84 txout[3] 126 i/o 168 i/o
13 ql80fc - quickfc tm pqfp 456 pinout table pbga 456 p inout t able 456 function 456 function 456 function 456 function 456 function a1 i/o b26 stm d25 i/o h4 i/o m14 gnd/therm a2 i/o c1 i/o d26 i/o h5 nc m15 gnd/therm a3 i/o c2 i/o e1 i/o h22 nc m16 gnd/therm a4 i/o c3 i/o e2 i/o h23 i/o m22 nc a5 i/o c4 tdo e3 i/o h24 i/o m23 nc a6 i/o c5 i/o e4 i/o h25 i/o m24 i/o a7 i/o c6 i/o e5 gnd h26 i/o m25 i/o a8 i/o c7 i/o e6 vcc j1 i/o m26 i/o a9 i/o c8 i/o e7 gnd j2 i/o n1 async_rst a10 i/o c9 i/o e8 nc j3 i/o n2 i/o a11 i/o c10 i/o e9 gnd j4 nc n3 i/o a12 vccio c11 i/o e10 i/o j5 gnd n4 resin[0] a13 i/o c12 i/o e11 gnd j22 nc n5 vcc a14 i/o c13 i/o e12 gnd j23 nc n11 gnd/therm a15 i/o c14 i/o e13 vcc j24 i/o n12 gnd/therm a16 i/o c15 i/o e14 gnd j25 i/o n13 gnd/therm a17 i/o c16 i/o e15 gnd j26 i/o n14 gnd/therm a18 i/o c17 i/o e16 gnd k1 i/o n15 gnd/therm a19 i/o c18 i/o e17 nc k2 i/o n16 gnd/therm a20 i/o c19 i/o e18 gnd k3 i/o n22 gnd a21 i/o c20 i/o e19 nc k4 i/o n23 i/o a22 i/o c21 i/o e20 gnd k5 vcc n24 i/o a23 i/o c22 i/o e21 vcc k22 gnd n25 i/o a24 i/o c23 i/o e22 gnd k23 i/o n26 i/o a25 i/o c24 i/o e23 i/o k24 i/o p1 i/o a26 i/o c25 tck e24 i/o k25 i/o p2 i/o b1 i/o c26 i/o e25 i/o k26 i/o p3 i/o b2 i/o d1 i/o e26 i/o l1 i/o p4 i/o b3 i/o d2 i/o f1 i/o l2 i/o p5 nc b4 i/o d3 i/o f2 i/o l3 i/o p11 gnd/therm b5 i/o d4 gnd f3 i/o l4 i/o p12 gnd/therm b6 i/o d5 i/o f4 nc l5 nc p13 gnd/therm b7 i/o d6 nc f5 vcc l11 gnd/therm p14 gnd/therm b8 i/o d7 i/o f22 vcc l12 gnd/therm p15 gnd/therm b9 i/o d8 i/o f23 nc l13 gnd/therm p16 gnd/therm b10 i/o d9 gnd f24 i/o l14 gnd/therm p22 nc b11 i/o d10 i/o f25 i/o l15 gnd/therm p23 resin[1] b12 i/o d11 i/o f26 i/o l16 gnd/therm p24 resin[2] b13 i/o d12 gnd g1 i/o l22 nc p25 i/o b14 i/o d13 i/o g2 i/o l23 i/o p26 aclk / i b15 i/o d14 i/o g3 i/o l24 i/o r1 i/o b16 i/o d15 gnd g4 i/o l25 i/o r2 i/o b17 i/o d16 i/o g5 nc l26 i/o r3 i/o b18 i/o d17 i/o g22 gnd m1 txclk125_in r4 nc b19 i/o d18 gnd g23 i/o m2 rxclk125_in r5 nc b20 i/o d19 i/o g24 i/o m3 i/o r11 gnd/therm b21 i/o d20 i/o g25 i/o m4 nc r12 gnd/therm b22 i/o d21 nc g26 i/o m5 gnd r13 gnd/therm b23 i/o d22 i/o h1 i/o m11 gnd/therm r14 gnd/therm b24 i/o d23 gnd h2 i/o m12 gnd/therm r15 gnd/therm b25 i/o d24 i/o h3 i/o m13 gnd/therm r16 gnd/therm
14 preliminary 14 ql80fc - quickfc tm 456 function 456 function 456 function 456 function r22 vcc y1 i/o ac6 nc ae5 rxin[3] r23 nc y2 i/o ac7 i/o ae6 rxin[4] r24 i/o y3 i/o ac8 i/o ae7 rxin[5] r25 i/o y4 i/o ac9 nc ae8 rxin[6] r26 gclk / i y5 i/o ac10 i/o ae9 rxin[7] t1 i/o y22 gnd ac11 i/o ae10 rxin[8] t2 i/o y23 i/o ac12 nc ae11 rxin[9] t3 i/o y24 i/o ac13 i/o ae12 i/o t4 i/o y25 i/o ac14 vccio ae13 txout[0] t5 vcc y26 i/o ac15 nc ae14 txout[2] t11 gnd/thermal aa1 i/o ac16 i/o ae15 txout[4] t12 gnd/thermal aa2 i/o ac17 i/o ae16 txout[6] t13 gnd/thermal aa3 nc ac18 nc ae17 txout[8] t14 gnd/thermal aa4 nc ac19 i/o ae18 txout[10] t15 gnd/thermal aa5 vcc ac20 i/o ae19 txout[12] t16 gnd/thermal aa22 vcc ac21 i/o ae20 txout[14] t22 gnd aa23 nc ac22 nc ae21 txout[16] t23 i/o aa24 i/o ac23 gnd ae22 txout[18] t24 i/o aa25 i/o ac24 i/o ae23 nc t25 i/o aa26 i/o ac25 i/o ae24 tms t26 i/o ab1 i/o ac26 i/o ae25 i/o u1 i/o ab2 i/o ad1 i/o ae26 i/o u2 i/o ab3 i/o ad2 nc af1 i/o u3 i/o ab4 i/o ad3 i/o af2 i/o u4 i/o ab5 gnd ad4 i/o af3 rxin[10] u5 gnd ab6 vcc ad5 i/o af4 rxin[11] u22 nc ab7 nc ad6 i/o af5 rxin[12] u23 i/o ab8 nc ad7 i/o af6 rxin[13] u24 i/o ab9 nc ad8 i/o af7 rxin[14] u25 i/o ab10 vcc ad9 i/o af8 rxin[15] u26 i/o ab11 gnd ad10 i/o af9 rxin[16] v1 i/o ab12 nc ad11 i/o af10 rxin[17] v2 i/o ab13 i/o ad12 rxcomdet af11 rxin[18] v3 i/o ab14 gnd ad13 i/o af12 rxin[19] v4 nc ab15 vcc ad14 i/o af13 txout[1] v5 nc ab16 i/o ad15 i/o af14 txout[3] v22 gnd ab17 nc ad16 i/o af15 txout[5] v23 nc ab18 vcc ad17 i/o af16 txout[7] v24 i/o ab19 gnd ad18 i/o af17 txout[9] v25 i/o ab20 nc ad19 i/o af18 txout[11] v26 i/o ab21 vcc ad20 i/o af19 txout[13] w1 i/o ab22 gnd ad21 i/o af20 txout[15] w2 i/o ab23 i/o ad22 i/o af21 txout[17] w3 i/o ab24 i/o ad23 trstb af22 txout[19] w4 i/o ab25 i/o ad24 i/o af23 i/o w5 nc ab26 i/o ad25 i/o af24 i/o w22 nc ac1 i/o ad26 i/o af25 i/o w23 i/o ac2 i/o ae1 tdi af26 i/o w24 i/o ac3 nc ae2 rxin[0] w25 i/o ac4 gnd ae3 rxin[1] w26 i/o ac5 i/o ae4 rxin[2]
15 ql80fc - quickfc tm timing diagrams figure 7. transmit timing diagram transmit timing characteristics figure 8. receive timing diagram receive timing characteristics t iming d iagrams parameter description min typ max units t1 clock to out 2.5 3.7 5.6 ns parameter description min typ max units t1 setup time 0.0 ns t2 hold time 2.3 1.5 ns
16 preliminary 16 ql80fc - quickfc tm figure 9. clock frequency ratios are dependent on tenbmode setting
17 ql80fc - quickfc tm reference development kit quicklogic has designed an evaluation board, which will allow the system designer to test their designs in hardware. the board plugs into a pci expansion slot in a windows pc and allows the user to communi- cate with the quicklogic endec chip via a user modifiable software script and the pci bus. the block diagram for the board is shown below. pci speeds of up to 64 bits at 75 mhz are supported via quick- logic's ql5064 device, enabling system read/write speeds matching those of the fibre channel link. there is a socket for the endec chip, and connec- tion points for a logic analyzer on the board. there is also a gbic fibre channel connector on the board to allow communication with other fibre channel devices. a reference design is supplied by quicklogic to load into the programmable portion of the endec chip. the reference design code will allow the sys- tem designer to immediately have an operational chip for use on the reference board. the source code for the reference design and software is available to the system designer for use or modification as he or she wishes, free of charge. figure 10. reference board block diagram r eference d evelopment k it pci bus transmit fifo receive fifo fifo control user customizable logic embedded fibre channel endec quicklogic ql80fc programmable endec chip glue logic for fifo interface transmit/ receive serdes gbic media i/o 2.5 gb/s quicklogic ql5064 75mhz/64 bit pci controller 125 mhz oscillator led indicators 8 bit data bus
18 preliminary 18 ql80fc - quickfc tm absolute maximum ratings vcc voltage . . . . . . . . . . . . . . . . -0.5 to 4.6v vccio voltage . . . . . . . . . . . . . . -0.5 to 7.0v input voltage . . . . . . . . -0.5v to vccio +0.5v latch-up immunity . . . . . . . . . . . . 200ma dc input current . . . . . . . . . . . . 20 ma esd pad protection . . . . . . . . . . . 2000v storage temperature . . . . . . -65 o c to + 150 o c lead temperature . . . . . . . . . . . . . . . . 300 o c operating range dc characteristics notes: [1] capacitance is sample tested only. [2] only one output at a time. duration should not exceed 30 seconds. [3] see application note 32: power calculations for quicklogic devices. symbol parameter industrial commercial unit min max min max vcc supply voltage 3.0 3.6 3.0 3.6 v vccio i/o input tolerance voltage 3.0 5.5 3.0 5.25 v ta ambient temperature -40 85 0 70 c k delay factor -a s p eed grade 0.43 0.90 0.46 0.88 symbol parameter conditions min max unit vih input high voltage 0.5vcc vccio+0.5 v vil input low voltage -0.5 0.3vcc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9vcc v vol output low voltage iol = 16 ma 0.45 v iol = 1.5 ma 0.1vcc v ii i or i/o input leakage current vi = vccio or gnd -10 10 a ioz 3-state out p ut leaka g e current vi = vccio or gnd -10 10 a ci input capacitance [1] 10 pf ios output short circuit current [2] vo = gnd -15 -180 ma vo = vcc 40 210 ma icc d.c. supply current [3] vi , vio = vccio or gnd 0.50 ( t yp) 2ma iccio d.c. supply current on vccio 0 100 a
19 ql80fc - quickfc tm ac characteristics at vcc = 3.3v, ta = 25 c (k = 1.00) (to calculate delays, multiply the appropriate k factor in the ? operating range ? section by the following numbers.) logic cells ram cell synchronous write timing notes: [4] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [5] these limits are derived from a representative selection of the slowest paths through the quickram logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analy- sis of your particular design. symbol parameter propagation delays (ns) fanout [5] 12348 tpd combinatorial delay [6] 1.4 1.7 1.9 2.2 3.2 tsu setup time [6] 1.7 1.7 1.7 1.7 1.7 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.7 1.0 1.2 1.5 2.5 tcwhi clock high time 1.2 1.2 1.2 1.2 1.2 tcwlo clock low time 1.2 1.2 1.2 1.2 1.2 tset set delay 1.0 1.3 1.5 1.8 2.8 treset reset delay 0.8 1.1 1.3 1.6 2.6 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) fanout [4] 12348 tswa wa setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwa wa hold time to wclk 0.0 0.0 0.0 0.0 0.0 tswd wd setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwd wd hold time to wclk 0.0 0.0 0.0 0.0 0.0 tswe we setup time to wclk 1.0 1.0 1.0 1.0 1.0 thwe we hold time to wclk 0.0 0.0 0.0 0.0 0.0 twcrd wclk to rd (wa=ra) [4] 5.0 5.3 5.6 5.9 7.1
20 preliminary 20 ql80fc - quickfc tm ram cell synchronous read timing ram cell asynchronous read timing input-only cells clock cells notes: [6] the array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 8 loads per half column. the global clock has up to 11 loads per half column. symbol parameter propagation delays (ns) fanout 12348 tsra ra setup time to rclk 1.0 1.0 1.0 1.0 1.0 thra ra hold time to rclk 0.0 0.0 0.0 0.0 0.0 tsre re setup time to rclk 1.0 1.0 1.0 1.0 1.0 thre re hold time to rclk 0.0 0.0 0.0 0.0 0.0 trcrd rclk to rd [5] 4.0 4.3 4.6 4.9 6.1 symbol parameter propagation delays (ns) fanout 12348 rpdrd ra to rd [5] 3.0 3.3 3.6 3.9 5.1 symbol parameter propagation delays (ns) fanout [5] 123481224 tin high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 tini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 tlrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 tlesu input register clock enable setup time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 propagation delays (ns) loads per half column [6] symbols parameter 12 3 48 101215 tack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 1.8 tgckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7 tgckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 1.4
21 ql80fc - quickfc tm i/o cell input delays i/o cell output delays notes: [7] the following loads are used for tpxz: symbol parameter propagation delays (ns) fanout [5] 1 2 34810 ti/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 tlorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.1 2.5 3.1 3.6 4.7 touthl output delay high to low 2.2 2.6 3.2 3.7 4.8 tpzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 tpzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 tphz output delay high to tri-state [8] 2.0 tplz output delay low to tri-state [8] 1.2 5 pf 1k ? 5 pf 1k ? tphz tplz

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